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The fifth network stage differs from the earlier ([[:Category:Quantum Memory Network Stage|Quantum Memory]]) stage by demanding that the local operations can be performed fault-tolerantly (without any error), which is considerably more challenging. The devices on the | The fifth network stage differs from the earlier ([[:Category:Quantum Memory Network Stage|Quantum Memory]]) stage by demanding that the local operations can be performed fault-tolerantly (without any error), which is considerably more challenging.The devices on the end nodes are not full fedged quantum computers but a smaller version of the same with fewer qubits than what is required to show quantum supremacy or efficiently do better than a classical computer. Fault tolerance implies that all error parameters of a quantum memory network can be made negligible by adding more resources. Here the number of qubits available is small enough such that the end nodes can be simulated effectively on a classical computer. Here, the main interest is the performance of the fault- | ||
tolerant scheme. However, this does not imply that the entire network can be simulated efficiently or that there would exist equivalent classical protocols; the effect of entanglement cannot generally be replicated classically.<br/> | |||
==Application== | |||
Having access to fault-tolerant gates allows higher-accuracy clock synchronization (3) and protocols that require many rounds of communication and high circuit depth to be useful. This includes distributed quantum computing as well as applications for full-scale quantum computing networks, restricted to few qubits. This could be of great practical interest, especially for applica- | |||
tions in the domain of distributed systems. | |||
quantum | ==Relevant Parameters== | ||
memory network can be made negligible by adding more resources. | |||
classical computer. Here, the main interest is the performance of the fault- | |||
tolerant scheme, | |||
of entanglement cannot generally be replicated classically. | |||
Having access to fault-tolerant gates allows higher-accuracy clock | |||
high circuit depth to be useful. This includes distributed quantum computing | |||
as well as applications for full-scale quantum computing networks, restricted | |||
to few qubits. This could be of great practical interest, especially for applica- | |||
tions in the domain of distributed systems | |||
[[Category:Network Stages]] | [[Category:Network Stages]] |